1. Field of the Invention
The invention relates to a semiconductor structure with the common source line, and is especially related to a common source line which has low sheet resistance, low cost, low side effect, and simple fabrication.
2. Description of the Prior Art
The common source line is a popular structure inside the semiconductor product, especially is broadly used by the memory cell, such as the flash memory. As shown in the brief top-view illustration FIG. 1A, common source line 10 usually is located between two gates 11, which are neighboring but separated, common source line 10 is electrically separated from these gates 11 but is coupled with some doped regions 12 inside substrate 13. For example, for some flash memory cell, two gates 11 are two word lines, some doped regions 12 are some bit lines, and common source lines 10 is used to control the state of some source (each source is a part of a bit line). Thus, usually several bit lines share a common source line which usually contacts with a source contact.
The function of common source line 10 is electrically coupled with some doped regions 12 which usually are located in and adjacent to the surface of substrate 13. Thus, as shown in FIG. 1B and FIG. 1C, both are the brief cross-section illustrations along AAxe2x80x2 of FIG. 1A, common source line 10 has two conventional structures. One conventional structure is shown in FIG. 1B, partial substrate 13 between neighboring doped regions 12 are transformed into conductive regions 14; another conventional structure is shown is FIG. 1C, metal layer 15 is formed on isolation layer 16 and directly electrically coupled with doped regions 12. Moreover, the material of metal layer 15 usually is tungsten which has smaller resistance, and both the material and the fabrication of conductive regions are changeable. For example, conductive regions 14 could be formed by directly implanting ions into substrate 13; conductive regions 14 also could be formed by firstly removing isolation layer 16 between neighboring doped regions 12 and then filling low resistance material to form required conductive regions 14.
Clearly, the application of conductive regions 14 at least has following defects: fabrication with removal of isolation layer 16 is too complicated, and fabrication with directly implantation inevitably affects the quality of the bit lines which usually also are doped regions. Further, the application of metal layer 15 at least has following defects: sometimes it is hard to form common source line 10 with high conductivity, and sometimes cost of common source line 10 with high conductivity is high, where the cost includes the material cost and the fabricating cost.
Accordingly, although the conventional technology has two available common source line structures, because none could simultaneously satisfy the requirements of low cost, low side effect and simple fabrication, it is desired to develop a new common source line structure.
One main object of this invention is providing a common source line with following advantages: low resistance, low cost, low side effect and simple fabrication.
Another main object of this invnetion is providing semiconductor structure which achieves high bit lines to source contact ratio by properly modifying the used common source line.
Yet one object of this invention is forming a conductive structure which connects some doped regions by applying the characteristics of the common source line which present by this invention.
The invention synthesizes the advantages of two conventional common source line structures. On one hand, this invention lets the common source line be located on the substrate to simply the corresponding fabrication and to reduce the side effect. On the other hand, this invention forms the common source line by using the silicon material that is cheaper than the metal such as tungsten. Further, it should be emphasized that the application of the silicon material let the invention could be incorporated with the self-alignment metal silicide fabricating process. Thus, the whole fabrication of the integrated circuits could be further simplified. And the metal silicide on the silicon material could be used to conduct the current for its resistance being lower than that of the silicon-based layer, and then the net resistance of the common source line which is made of both silicon and metal silicide could be further reduced.